With continuous development of integrated circuit (IC) manufacturing technology, feature size of metal-oxide-semiconductor (MOS) transistors becomes smaller. As process node shrinks, thickness of gate dielectric layers (e.g., silicon oxide) is continuously reduced. The increased thickness of the gate dielectric layer increases the leakage current of the MOS transistors exponentially. Therefore, using silicon oxide as a gate dielectric layer no longer meets requirements for high-speed IC development. Gate stack structures including a high-K dielectric layer and a metal gate electrode have been introduced into the MOS transistors to replace gate stack structures based on a silicon oxide layer and a polysilicon electrode.
Existing methods for forming a high-K dielectric layer include a physical vapor deposition process (PVD) and a chemical vapor deposition process (CVD). The CVD process includes an atomic layer deposition (ALD) process and a metal organic chemical vapor deposition (MOCVD).
An ALD process for forming a high-K dielectric layer, e.g., a high-K hafnium oxide layer, may include: placing a semiconductor substrate in an ALD chamber; pulsing a first precursor, such as H2O, into the ALD chamber; purging residues of the first precursor and a first reaction product; introducing a second precursor, such as hafnium tetrachloride, into the ALD chamber; and purging residues of the second precursor and a second reaction product. This process is repeatedly performed until a high-K dielectric layer of hafnium oxide forms on the semiconductor substrate.
However, when such existing ALD process is used to form high-K dielectric layers, it is difficult to form high-K dielectric layers with different thicknesses at different regions of a semiconductor substrate, unable to satisfy the requirements for manufacturing semiconductor devices.